The present invention relates to high speed pipeline data processing systems and, in particular, to a pipelined floating point execution unit utilizing ideal operand manipulation condition detection for the selection of optimal execution flow.
High speed data processing systems typically are provided with high-speed floating point units that perform floating point operations such as add, subtract, compare, and multiply. These systems typically utilize a pipelined architecture providing for a multistaged data flow that is controlled at each stage by control logic.
The multiple stage pipelined architecture allows multiple instructions to be processed concurrently in the pipeline. Generally, the instructions in the pipeline have a one stage offset from one another thereby optimizing the utilization of available hardware. Each instruction typically progresses from one stage to the next successive stage with each clock cycle.
The actual data flow through the instruction pipeline is controlled within each stage, for example, by micro-code stored in a control store. The instruction itself addresses the control store to select a corresponding micro-code control word. The control word, in turn, enables specific data paths to perform the desired data manipulation.
Each stage of the pipeline implements a substantial number of functions in parallel, thus minimizing the number of stages required to implement any given instruction. The instruction execution speed of pipelined data processing systems is typically greater than comparable non-pipelined systems utilizing a similar number of execution stages. Enhancements in the execution speed of such pipelined systems is naturally desirable.